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April 1997
ML4890
High Efficiency, Low Ripple Boost Regulator
GENERAL DESCRIPTION
The ML4890 is a high efficiency, PFM (Pulse Frequency Modulation), boost switching regulator connected in series with an integrated LDO (Low Dropout Regulator) that incorporates "Silent SwitcherTM" technology. This technique incorporates a patented tracking scheme to minimize the voltage drop across the LDO and increase the total efficiency of the regulator beyond that which can be obtained by using a discrete external LDO regulator. The ML4890 is designed to convert single or multiple cell battery inputs to regulated output voltages for integrated circuits and is ideal for portable communications equipment that cannot tolerate the output voltage ripple normally associated with switching regulators. An integrated synchronous rectifier eliminates the need for an external Schottky diode and provides a lower forward voltage drop, resulting in higher conversion efficiency.
FEATURES
s s
Incorporates "Silent SwitcherTM" technology to deliver very low output voltage ripple (typically 5mV) Guaranteed full load start-up and operation at 1.0V input and low operating quiescent current (<100A) for extended battery life Pulse Frequency Modulation and internal synchronous rectification for high efficiency Minimum external components Low ON resistance internal switching MOSFETs 5V, 3.3V, and 3V output versions
s s s s
BLOCK DIAGRAM
L1
*CIN
VIN
C2 1 VL 6 5 VBOOST
VBAT 7
SHDN VOUT 4 BOOST CONTROL FEEDBACK LDO CONTROL C1 VOUT +
2
VREF
3 FROM POWER MANAGEMENT
GND
PWR GND
8
-
Patent Pending *Optional
1
ML4890
PIN CONNECTION
ML4890-5/-3/-T 8-Pin SOIC (S08)
VIN VREF GND VOUT
1 2 3 4
8 7 6 5
PWR GND SHDN VL VBOOST
TOP VIEW
PIN DESCRIPTION
PIN NO. PIN NO.
NAME
FUNCTION
NAME
FUNCTION
1 2 3 4
VIN VREF GND VOUT
Battery input voltage 200mV reference output Analog signal ground LDO linear regulator output
5 6 7
VBOOST VL SHDN
Boost regulator output for connection of an output filter capacitor Boost inductor connection Pulling this pin high shuts down the regulator, isolating the load from the input
8
PWR GND Return for the NMOS boost transistor
2
ML4890
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VBOOST ........................................................................ 7V Voltage on Any Other Pin ... GND -0.3V to VBOOST +0.3V Peak Switch Current (IPEAK) .......................................... 1A Average Switch Current (IAVG) ............................... 500mA LDO Output Current ............................................. 250mA Junction Temperature .............................................. 150C Storage Temperature Range .................... -65C to +150C Lead Temperature (Soldering 10s) .......................... +260C Thermal Resistance (JA) Plastic SOIC .................................................... 110C/W
OPERATING CONDITIONS
Temperature Range ML4890CS-X ............................................ 0C to +70C ML4890ES-X ......................................... -20C to +70C VIN Operating Range ML4890CS-X ................................................ 1.0V to 6V ML4890ES-X ................................................. 1.1V to 6V
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VIN = Operating Voltage Range, TA = Operating Temperature Range. (Note 1)
PARAMETER Supply VIN Current VIN = 6V SHDN = high VOUT Quiescent Current VL Quiescent Current Reference Output Voltage (VREF) PFM Regulator Pulse Width (TON) LDO DC Output Voltage (VOUT) ML4890-5 ML4890-3 ML4890-T Load Regulation ML4890-5 VBOOST = VOUT + 0.5V, IOUT < 200mA VBOOST = VOUT + 0.5V, IOUT < 100mA VBOOST = VOUT + 0.5V, IOUT < 80mA See Figure 1 VIN = 1.2V, IOUT < 7mA VIN = 2.4V, IOUT < 50mA VIN = 1.2V, IOUT < 14mA VIN = 2.4V, IOUT < 75mA VIN = 1.2V, IOUT < 15mA VIN = 2.4V, IOUT < 60mA See Figure 1 VIN = 1.2V, IOUT < 7mA VIN = 2.4V, IOUT < 50mA VIN = 1.2V, IOUT < 14mA VIN = 2.4V, IOUT < 75mA VIN = 1.2V, IOUT < 15mA VIN = 2.4V, IOUT < 60mA 5 4.85 3.2 2.91 4.85 4.85 3.2 3.2 2.91 2.91 5.0 3.3 3.0 5.0 5.0 3.3 3.3 3.0 3.0 5.15 3.4 3.09 5.15 5.15 3.4 3.4 3.09 3.09 300 500 300 500 300 500 V V V V V V V V V mV mV mV mV mV mV mVP-P 4.5 5 5.5 s 0 < IPIN2 < -5A, 195 200 205 mV VBOOST = VOUT + 0.5V 60 15 8 75 25 10 1 A A A A CONDITIONS MIN TYP. MAX UNITS
ML4890-3 ML4890-T Dropout Voltage ML4890-5
ML4890-3 ML4890-T Output Ripple Shutdown SHDN Threshold SHDN Bias Current
Note 1:
0.5 -100
0.8
1.0 100
V nA
Limits are guaranteed by 100% testing, sampling, or correlation with worst case conditions.
3
ML4890
33H (Sumida CD54)
ML4890
VIN 100F VIN VREF 1F GND VOUT PWR GND SHDN VL VBOOST 33F
IOUT VOUT 100F
Figure 1. Application Test Circuit
L1 6 5
C2 ILOAD 4 Q2 Q3 + A2 - A3 - VREF R2 + R1 C1
R S
5s ONE SHOT
Q1
A1
- + +- VOS = f (ILOAD)
Figure 2. PFM Regulator and LDO Block Diagram
4
ML4890
FUNCTIONAL DESCRIPTION
The ML4890 combines Pulse Frequency Modulation (PFM) and synchronous rectification to create a boost converter that is followed by a low dropout linear regulator (LDO). This combination creates a low output ripple boost converter that is both highly efficient and simple to use. The PFM regulator charges a single inductor for a fixed period of time and then completely discharges before another cycle begins, simplifying the design by eliminating the need for conventional current limiting circuitry. Synchronous rectification is accomplished by replacing an external Schottky diode with an on-chip PMOS device, reducing switching losses and external component count. The integrated LDO reduces the output ripple voltage to less than 5mV peak-to-peak. Integrating the LDO along with the PFM regulator allows the circuit to be optimized for very high efficiency using a patented feedback technique. It also allows the LDO to provide the maximum ripple rejection over the operating frequency range of the regulator. A block diagram of the ML4890 is shown in Figure 2. The PFM stage is comprised of Q1, Q2, A1, A2, the one shot, the flip-flop, and externals L1 and C2. The LDO stage is comprised of Q3, A3, R1, R2, the offset voltage control, and external C1. Since the LDO actually controls the operation of the PFM regulator, the operation of the LDO stage will be covered first. LDO OPERATION The LDO stage operates as a linear regulator. A3 is the error amplifier, which compares the output voltage through the divider R1 and R2 to the reference, and Q3 is the pass device. When the output voltage is lower than desired, the output of A3 increases the gate drive of Q3, which reduces the voltage drop across it and brings the output back into regulation. Similarly, if the output voltage is higher than desired, A3 adjusts the gate drive of Q3 for more drop and the output is brought back into regulation.
450 400 350 300 250 200 150 100
Also included in the LDO stage is an offset voltage control. This circuit monitors the output current and adjusts the offset voltage according the general characteristic shown in Figure 3. The offset control ensures that the PFM stage provides just enough "overhead" voltage for the LDO stage to operate properly. PFM REGULATOR OPERATION When the output of the PFM stage, VBOOST (pin 5), is at or above the dropout voltage, VOUT + VOS, the output of A1 stays low and the circuit remains idle. When VBOOST falls below the required dropout voltage, the output of A1 goes high, signaling the regulator to deliver charge to the capacitor C2. Since the output of A2 is normally high, the output of the flip-flop becomes SET. This triggers the one shot to turn Q1 on and begins charging L1 for 5s. When the one shot times out, Q1 turns off, allowing L1 to flyback and momentarily charge C2 through the body diode of Q2. But, as the source voltage of Q2 rises above the drain, the current sensing amplifier A2 drives the gate of Q2 low, causing Q2 to short out the body diode. The inductor then discharges into C2 through Q2. The output of A2 going low also serves to RESET the flip-flop in preparation for the next charging cycle. When the inductor current in Q2 falls to zero, the output of A2 goes high, releasing Q2`s gate, allowing the flip-flop to be SET again. If the voltage at VBOOST is still low, A1 will initiate another pulse. Typical inductor current and voltage waveforms are shown in Figure 4.
INDUCTOR CURRENT
Q(ONE SHOT)
Q1 ON Q1 & Q2 OFF
Q2 ON
Q1 ON
Q2 ON
Figure 4. PFM Inductor Current Waveforms and Timing. SHUTDOWN The SHDN pin should be held low for normal operation. Raising the voltage on SHDN above the threshold level will release the gate of Q3, which effectively becomes an open circuit. This also prevents the one shot from triggering, which keeps switching from occurring.
VOS (mV)
0
10
20
30
40
50
60
70
80
90 100
IOUT (mA)
Figure 3. LDO VOS versus output current.
5
ML4890
DESIGN CONSIDERATIONS
INDUCTOR Selecting the proper inductor for a specific application usually involves a trade-off between efficiency and maximum output current. Choosing too high a value will keep the regulator from delivering the required output current under worst case conditions. Choosing too low a value causes efficiency to suffer. It is necessary to know the maximum required output current and the input voltage range to select the proper inductor value. The maximum inductor value can be estimated using the following formula: where is the efficiency, typically between 0.75 and 0.85, and VOS is the dropout voltage at IOUT(MAX) taken from Figure 3. Note that this is the value of inductance that just barely delivers the required output current under worst case conditions. A lower value may be required to cover inductor tolerance, the effect of lower peak inductor currents caused by resistive losses, and minimum dead time between pulses. Another method of determining the appropriate inductor value is to make an estimate based on the typical performance curves given in Figures 5 and 6. Figure 5 shows maximum output current as a function of input voltage for several inductor values. These are typical performance curves and leave no margin for inductance and ON-time variations. To accommodate worst case conditions, it is necessary to derate these curves by at least 10% in addition to inductor tolerance.
LMAX =
VIN(MIN) x TON(MIN) x 2 x (VOUT + VOS ) x IOUT(MAX)
2
(1)
80 70
ML4890-T
H
H
H
100
ML4890-3
H
L
33 H
=
L=
L=
=
90 80 70
L=
L=
L
L
=
22
15
22
10
10
47
H
H
H
IOUT MAX (mA)
IOUT MAX (mA)
50 40 30 20 10 0 1.0
L
=
L=
60
H 68
15
L
=
33
H
L
=
=
47
H
60 50 40 30 20 10
L
H 68
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
0 1.0
1.5
2.0 VIN (V)
2.5
3.0
VIN (V)
200 180 160 140
IOUT MAX (mA)
ML4890-5
L= 22 H
L
15 L=
120 100
H
H
L
80 60 40 20 0 1.0
L=
L=
1.5
10
2.0
2.5
3.0
3.5
4.0
=
=
33
H 47
H 68
H
4.5
VIN (V)
Figure 5. Output Current versus Input Voltage.
6
ML4890
For example, a two cell to 5V application requires 40mA of output current while using an inductor with 15% tolerance. The output current should be derated by 25% to 50mA to cover the combined inductor and ON-time tolerances. Assuming that 2V is the end of life voltage of a two cell input, Figure 5 shows that with a 2V input, the ML4890-5 delivers 58mA with a 22H inductor. Figure 6 shows efficiency under the conditions used to create Figure 5. It can be seen that efficiency is mostly independent of input voltage and is closely related to inductor value. This illustrates the need to keep the inductor value as high as possible to attain peak system efficiency. As the inductor value goes down to 10H, the efficiency drops to between 70% and 75%. With 33H, the efficiency reaches approximately 85% and there is little room for improvement. At values greater than 47H, the operation of the synchronous rectifier becomes unreliable at low input voltages because the inductor current is so small that it is difficult for the control circuitry to detect. The data used to generate Figures 5 and 6 is provided in Table 1. After the appropriate inductor value is chosen, it is necessary to find the minimum inductor current rating required. Peak inductor current is determined from the following formula:
IL(PEAK ) =
TON(MAX) x VIN(MAX) LMIN
(2)
It is important to note that for reliable operation, make sure that IL(PEAK) does not exceed the 1A maximum switch current rating. In the two cell application previously described, a maximum input voltage of 3V would give a peak current of 880mA. When comparing various inductors, it is important to keep in mind that suppliers use different criteria to determine their ratings. Many use a conservative current level, where inductance has dropped to 90% of its normal level. In any case, it is a good idea to try inductors of various current ratings with the ML4890 to determine which inductor is the best choice. Check efficiency and maximum output current, and if a current probe is available, look at the inductor current to see if it looks like the waveform shown in Figure 4.
95
95
ML4890-T
Efficiency at IOUT MAX (%)
L = 68H
ML4890-3
Efficiency at IOUT MAX (%)
90
90 L = 47H 85 L = 33H 80 L = 22H L = 15H 75 L = 10H 70
L = 68H
L = 47H
85
L = 33H
80
L = 22H
L = 15
75
H
L=1
70
0H
65 1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
65 1.0
1.5
2.0 VIN (V)
2.5
3.0
VIN (V)
95
ML4890-5
L = 68H
L = 47H
Efficiency at IOUT MAX (%)
90 85 80 75 L = 10H 70 65 60 1.0
L = 15
H
L = 22
L = 33H
H
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Figure 6. Typical Efficiency as a Function of VIN.
7
ML4890
The DC resistance of the inductor should be kept to a minimum to reduce losses. A good rule of thumb is to allow 5 to 10m of resistance for each H of inductance. Also, be aware that the DC resistance of an inductor usually isn`t specified tightly, so an inductor with a maximum DC resistance spec of 150m may actually have 100m of resistance. Suitable inductors can be purchased from the following suppliers: Coilcraft Coiltronics Dale Sumida BOOST CAPACITOR The boost capacitor (C2) supplies current to the load during the ON-time of Q1 and will limit the ripple the LDO stage has to contend with. The ripple on C2 is influenced by three capacitor parameters: capacitance, ESL, and ESR. The contribution due to capacitance can be determined by looking at the change in the capacitor voltage required to store the energy delivered by the inductor in a single charge-discharge cycle, as given by the following formula: (708) 639-6400 (407) 241-7876 (605) 665-9301 (708) 956-0666 For example, a 2.4V input, a 22H inductor, and an allowance of 100mV of ripple on the boost capacitor results in a maximum ESR of 200m. Therefore, a boost capacitor with a capacitance of 22F or 33F, an ESR of less than 200m, and an ESL of less than 5nH is a good choice. Tantalum capacitors which meet these requirements can be obtained from the following suppliers: AVX Sprague OUTPUT CAPACITOR The LDO stage output capacitor (C1) is required for stability and to provide a high frequency filter. An output capacitor with a capacitance of 100F, an ESR of less than 100m, and an ESL of less than 5nH is a good general purpose choice. INPUT CAPACITOR Unless the input source is a very low impedance battery, it will be necessary to decouple the input with a capacitor with a value of between 47F and 100F. This provides the benefits of preventing input ripple from affecting the ML4890 control circuitry, and it also improves efficiency by reducing I-squared R losses during the charge and discharge cycles of the inductor. Again, a low ESR capacitor (such as tantalum) is recommended. REFERENCE CAPACITOR Under some circumstances input ripple cannot be reduced effectively. This occurs primarily in applications where inductor currents are high, causing excess output ripple due to "pulse grouping", where the chargedischarge pulses are not evenly spaced in time. In such cases it may be necessary to decouple the reference pin (VREF) with a small 10nF to 100nF ceramic capacitor. This is particularly true if the ripple voltage at VIN is greater than 100mV. (207) 282-5111 (207) 324-4140
TON x VIN C2 (in Farads) 2 x L x VBOOST x (VOUT - VIN)
2
2
(3)
For example, a 2.4V input, a 5V output, a 22H inductor, and an allowance of 100mV of ripple on the boost capacitor results in a minimum C2 value of 15F. The boost capacitor`s Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL), also contribute to the ripple due to the inductor discharge current waveform. Just after the NMOS transistor turns off, the output current ramps quickly to match the peak inductor current. This fast change in current through the boost capacitor`s ESL causes a high frequency (5ns) spike that can be over 1V in magnitude. After the ESL spike settles, the boost voltage still has a ripple component equal to the inductor discharge current times the ESR. This component will have a sawtooth waveshape and can be calculated using the following formula:
ESR VBOOST (in ) IL(PEAK )
(4)
8
ML4890
LAYOUT
Good PC board layout practices will ensure the proper operation of the ML4890. Important layout considerations include: * Use adequate ground and power traces or planes * Keep components as close as possible to the ML4890 * Use short trace lengths from the inductor to the VL pin and from the output capacitor to the VBOOST pin. * Use a single point ground for the ML4890 ground pins, and the input and output capacitors A sample PC board layout is shown in Figure 7.
Figure 7. Sample PC Board Layout.
9
ML4890
TABLE 1. MAXIMUM OUTPUT CURRENT AND EFFICIENCY
ML4890-T
VIN L = 10H 1.0 1.5 2.0 L = 15H 1.0 1.5 2.0 2.5 2.8 L = 22H 1.0 1.5 2.0 2.5 2.8 L = 33H 1.0 1.5 2.0 2.5 2.8 L = 47H 1.0 1.5 2.0 2.5 2.8 L = 68H 1.0 1.5 2.0 2.5 2.8 IOUT (mA) 30.6 70.7 80.0 23.8 56.5 80.0 80.0 80.0 18.4 44.2 76.6 80.0 80.0 13.0 32.4 56.6 80.0 80.0 9.8 23.3 41.1 62.9 77.4 7.9 18.8 33.4 51.0 64.3 EFFICIENCY PERCENTAGE 73.5 72.0 70.3 78.7 77.3 74.9 74.0 73.7 82.0 81.1 77.9 76.9 76.7 85.7 85.1 82.7 80.4 80.1 87.4 87.2 85.8 83.7 82.6 88.4 88.9 87.6 86.0 84.6
ML4890-3
VIN L = 10H 1.0 1.5 2.0 L = 15H 1.0 1.5 2.0 2.5 3.0 L = 22H 1.0 1.5 2.0 2.5 3.0 L = 33H 1.0 1.5 2.0 2.5 3.0 L = 47H 1.0 1.5 2.0 2.5 3.0 L = 68H 1.0 1.5 2.0 2.5 3.0 IOUT (mA) 29.6 71.4 100.0 23.0 54.7 89.8 100.0 100.0 16.2 41.4 75.6 100.0 100.0 10.9 30.4 55.8 82.5 100.0 9.1 22.7 41.9 63.3 89.6 7.7 17.9 32.1 48.8 69.6 EFFICIENCY PERCENTAGE 73.8 73.7 71.9 80.4 78.8 76.1 74.7 74.1 82.1 82.6 80.5 77.7 77.1 85.0 86.0 84.7 82.3 80.3 87.1 87.9 87.4 85.6 83.1 89.3 89.2 88.3 87.2 85.9
10
ML4890
TABLE 1. MAXIMUM OUTPUT CURRENT AND EFFICIENCY
ML4890-5
VIN L = 10H 1.0 1.5 2.0 L = 15H 1.0 1.5 2.0 2.5 3.0 L = 22H 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 L = 33H 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 L = 47H 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 L = 68H 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 IOUT (mA) 13.6 42.7 82.2 9.3 31.7 60.6 95.7 137.9 7.4 23.1 46.1 73.9 108.9 145.1 184.5 200.0 6.0 18.3 34.2 57.0 82.3 106.0 137.1 169.3 EFFICIENCY PERCENTAGE 67.9 77.2 78.1 69.6 80.9 81.6 80.5 79.4 73.6 83.6 84.6 84.0 83.0 82.4 81.3 80.1 76.9 85.8 86.8 86.6 86.2 85.3 84.6 84.0
(continued)
14.2 25.7 41.4 59.4 82.9 105.5 131.3
87.2 88.3 88.3 88.0 87.3 86.6 86.2
17.9 31.7 46.2 63.2 82.5 99.7
88.9 89.8 89.7 89.6 89.2 88.0
11
ML4890
PHYSICAL DIMENSIONS inches (millimeters)
Package: S08 8-Pin SOIC
8 0.189 - 0.199 (4.80 - 5.06)
PIN 1 ID
0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20)
0.017 - 0.027 (0.43 - 0.69) (4 PLACES)
1 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0 - 8
0.055 - 0.061 (1.40 - 1.55)
0.012 - 0.020 (0.30 - 0.51) SEATING PLANE
0.004 - 0.010 (0.10 - 0.26)
0.015 - 0.035 (0.38 - 0.89)
0.006 - 0.010 (0.15 - 0.26)
ORDERING INFORMATION
PART NUMBER ML4890CS-T ML4890CS-3 ML4890CS-5 ML4890ES-T ML4890ES-3 ML4890ES-5 OUTPUT VOLTAGE 3.0V 3.3V 5.0V 3.0V 3.3V 5.0V TEMPERATURE RANGE 0C to +70C 0C to +70C 0C to +70C -20C to +70C -20C to +70C -20C to +70C PACKAGE 8-Pin SOIC (S08) 8-Pin SOIC (S08) 8-Pin SOIC (S08) 8-Pin SOIC (S08) 8-Pin SOIC (S08) 8-Pin SOIC (S08)
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
DS4890-01
12

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